Computer systems typically include devices or modules that communicate with a processor using a bus. One example of such a module might be a memory module. The bus is essentially a transmission line that carries signals such as clock, data, control, and address signals between the processor, modules, and other bus devices.
The bus architecture must be flexible enough to permit removal or addition of modules. For example, a processor might be located on a motherboard or backplane. Other boards (daughter boards) or modules, such as memory expansion modules, are then plugged into a socket on the motherboard. The socket connects a bus on the module to the motherboard bus when the module is plugged in. Thus the motherboard bus has been extended by the bus on the module. The bus (i.e., the motherboard and module buses collectively) needs to be able to accurately distribute precisely timed signals with or without such modules.
The timing and distribution of signals is often of critical importance in the computer system. However, as with other types of transmission lines, signal reflection may frustrate signal timing and distribution. Signal reflections are created when the bus interfaces with a component that has an impedance which differs from the characteristic impedance of the bus, such as a module. In other words, impedance discontinuities on the bus will generate reflections. Ideally, if the module impedance is matched with the characteristic impedance of the bus, there will be no reflections. However, when the impedances are not matched, the resulting reflections tend to degrade the computer system performance.
In particular, signal reflections can have a detrimental effect on the speed and operation of the computer system. The devices communicating on the bus might have to wait until the reflections have subsided before accepting any signal from the bus as valid. This waiting period tends to slow the system down. Alternatively, if a sufficient waiting period has not elapsed, then signal reflections might be misinterpreted as valid signals resulting in unpredictable operation of the system.
One prior art method of decreasing the effect of reflections requires the use of terminators. A terminator is a dissipative load, typically a resistor, located at the end of a transmission line. The terminator is chosen to have an impedance that matches the characteristic impedance of the transmission line. Prior art termination architectures include series termination and parallel termination.
In series termination, the terminating resistor is placed in series with the device driving the transmission line. In parallel termination, the device drives the transmission line directly and a terminator is placed at one or both ends of the transmission line. A bus with a parallel termination at one end of the bus is referred to as a single parallel termination bus. Alternatively such a bus may be called a singly terminated bus. A bus with parallel terminations at both ends is referred to as a double parallel termination bus. Alternatively such a bus may be called a doubly terminated bus.
In one prior art singly terminated bus, the terminator is replaced with an extended bus segment containing a terminator. The extended bus segment includes the expansion modules. In another prior art singly terminated bus, all expansion sockets on the bus are populated with either a functional module or a "dummy module". The functional module is a module such as a memory expansion module. The dummy module in this case is a module designed to provide the same effective load as a functional module. Thus in either of these cases the bus is always maintained as a singly terminated bus either with or without the modules.
Double parallel termination is commonly used in high speed bus architectures. In one prior art doubly terminated bus architecture, modules are plugged into or removed from a doubly terminated bus. The modules effectively tap into the bus. Bus discontinuities will result whenever a tap does not have a module plugged into it. In some cases the modules are inserted or removed regardless of the impedance mismatch. One disadvantage of this technique is the degradation of system performance as described above. Alternatively, the taps can be populated with dummy modules. One disadvantage of this technique is the complication and cost of additional dummy modules. Thus the bus is effectively maintained as a double parallel termination bus. One disadvantage of such a system is that dummy modules must be available to replace the removed modules.
In one prior art doubly terminated bus, the modules include bus segments that are daisy-chained together as more modules are added to the system. The modules are connected onto a bus already having a terminator. The last module would have to be a dummy module having a second terminator. This architecture always requires a dummy terminator module as the last module in the chain. In addition to the disadvantage of requiring the dummy module, this architecture requires "shuffling" the dummy module to another location every time the number of modules on the bus changes.